SY10/100E141 is an 8-bit full-function shift register designed for use in new, high-performance ECL systems. E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0–D7 accept parallel input data, while DL/DR accept serial input data for left/right shifting. The two select pins, SEL0 and SEL1 permit four modes of operation: Load, Hold, Shift Left and Shift Right, as shown in the Truth Table. Input data is clocked into the register on the rising clock edge after meeting the minimum set-up time. A logic HIGH on the Master Reset (MR) pin asynchronously resets all the registers to zero.
The SY10E141 and SY100E141 are 8‑bit, full‑function shift registers with bi‑directional data flow and four selectable modes (Load, Hold, Shift Left, Shift Right). They operate at shift frequencies from 700 MHz up to 900 MHz and are compatible with standard ECL voltage levels.
This document includes a block diagram, pin configuration, truth table, DC and AC electrical characteristics, package dimensions, and ordering codes for commercial versions. It serves as a reference for designers integrating the device into high‑performance ECL systems.
| Maximum Shift Frequency | 700 MHz min, 900 MHz typ |
|---|---|
| Input HIGH Current | 150 µA max |
| Power Supply Current (SY10E141) | 131 mA typ |
| Reset Recovery Time | 900 ps max |
| Minimum Pulse Width | 400 ps |
| Package | 28‑pin PLCC |
The device can shift at frequencies from 700 MHz minimum up to 900 MHz typical.
It supports four selectable modes: Load, Hold, Shift Left, and Shift Right.
The commercial ordering code is SY10E141JC.