The XC95144 is a high-performance CPLD from Altera that provides advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns.
The XC95144 is a high‑performance CPLD offering in‑system programming, 144 macrocells, and up to 3,200 usable gates. It supports 7.5 ns pin‑to‑pin logic delays, up to 133 user I/O pins, and a range of voltage options (3.3 V or 5 V I/O). The device includes extensive JTAG support and programmable power‑reduction modes.
The handbook lists detailed electrical specifications, timing parameters, absolute maximum ratings, and ordering options. It also provides guidance on power management, pin configurations, and package types (PQ100, TQ100, PQ160) for both commercial and industrial temperature ranges.
| Pin‑to‑pin logic delay | 7.5 ns |
|---|---|
| Number of macrocells | 144 |
| Usable gates | 3,200 |
| VCCINT supply voltage | 4.75 V – 5.25 V |
| VCCIO supply voltage (5 V operation) | 4.75 V – 5.25 V |
| Program/Erase endurance | 10,000 cycles |
| Industrial temperature range | -40 °C to +85 °C |
The XC95144 has a 7.5 ns pin‑to‑pin logic delay on all pins.
The device contains 144 macrocells providing up to 3,200 usable gates.
The XC95144 is rated for 10,000 program/erase cycles.
Commercial versions operate from 0 °C to 70 °C, while industrial versions operate from –40 °C to +85 °C.