DS050 is a high-performance FPGA chip with 288 macrocells, 6400 usable gates, and small packages, including 144-pin TQFP (117 user I/O pins), 208-pin PQFP (168 user I/O pins), 280-pin CSP (192 user I/O pins), and 256-pin FBGA (192 user I/O pins). The chip is optimized for high-performance 2.5V systems, low power operation, and multi-voltage operation. The chip also has excellent system features, including in-system programmable, four separate output banks, FastCONNECT II™ switch matrix, extra wide 54-input Function Blocks, up to 90 product-terms per macrocell with individual product-term allocation, three global and one product-term clocks for local clock inversion, individual output enable per output pin, input hysteresis on all user and boundary-scan pin inputs, bus-hold circuitry on all user pin inputs, full IEEE Standard 1149.1 boundary scan (JTAG) function, fast concurrent programming, slew rate control on individual outputs, enhanced data security features. The chip has excellent quality and reliability, with endurance exceeding 10,000 program/erase cycles, data retention of 20 years, and ESD protection exceeding 3000V/m.
The XC95288XV is a high-performance, low-voltage complementary programmable logic device (CPLD) designed for leading-edge communications and computing systems. It features 16 Function Blocks providing 6,400 usable gates with propagation delays of 5 ns.
| Macrocells | 288 |
|---|---|
| Usable Gates | 6,400 |
| Propagation Delay | 5 ns |
| Supply Voltage (VCC) | 2.37 to 2.62 V |
| Data Retention | 20 Years |
| Program/Erase Cycles | 10,000 |
| ESD Protection | 2,000 V |
The typical operating supply current in low power mode with no load at 1.0 MHz is 59 mA.
Yes, the XC95288XV is fully in-system programmable.