This document describes the features and characteristics of Xilinx's DS057 (v1.1) product. The product has a pin-to-pin logic delay of 5ns and a system frequency of up to 178MHz. It includes 72 macrocells and 1600 usable gates. The product is optimized for high-performance 3.3V systems and offers low power operation and 5V tolerant I/O pins. It supports in-system programmability, with superior pin-locking and routability using the FastCONNECT II switch matrix. The product also features wide function blocks, individual output enable per pin, input hysteresis, bus-hold circuitry, and full IEEE Standard 1149.1 boundary-scan (JTAG) support. Fast concurrent programming and slew rate control are also available.
The XC9572XL is a 3.3V CPLD designed for high-performance, low-voltage applications in communications and computing systems. It features four 54V18 Function Blocks providing 1,600 usable gates with propagation delays of 5ns and supports system frequencies up to 178 MHz. The device is available in various packages including PLCC, VQFP, CSP, and TQFP, offering optimized performance for 3.3V systems with 5V tolerant I/O pins.
| Logic Delays | 5ns pin-to-pin |
|---|---|
| System Frequency | up to 178 MHz |
| Macrocells | 72 |
| Usable Gates | 1,600 |
| Data Retention | 20 years |
| Program/Erase Cycles | 10,000 |
| ESD Protection | 2,000V |
| Operating Temperature (Commercial) | 0°C to 70°C |
| Operating Temperature (Industrial) | -40°C to +85°C |
The system frequency can reach up to 178 MHz.
It contains 1,600 usable gates.
Yes, its I/O pins are 5V tolerant and accept 5 V, 3.3V, and 2.5V signals.
The device has an endurance exceeding 10,000 program/erase cycles.