Key facts
- Brand
- Xilinx
- Model
- XC95144
- Category
- Other Electronics
- Documents
- 2
- Languages
- EN
- Last added
- 2012-06-08
Start here
ManualXILINX XC95144XV High-Performance CPLD Data Sheet
XILINX XC95144XV High-Performance CPLD Data Sheet
The document describes the features of the XC95144XV chip in detail, including 144 macro cells, 3200 usable gates, optimized design, etc.
Read onlineXilinx XC95144 specifications
| Pin‑to‑pin logic delay | 7.5 ns |
|---|---|
| Number of macrocells | 144 |
| Usable gates | 3,200 |
| VCCINT supply voltage | 4.75 V – 5.25 V |
| VCCIO supply voltage (5 V operation) | 4.75 V – 5.25 V |
| Program/Erase endurance | 10,000 cycles |
| Industrial temperature range | -40 °C to +85 °C |
Source: Xilinx XC95144 CPLD Handbook
All Xilinx XC95144 documents by type
Datasheet 1
Ratings, dimensions and ordering codes, for selection and design work.
Other documents 1
Questions answered in these manuals
What is the pin‑to‑pin logic delay of the XC95144?
The XC95144 has a 7.5 ns pin‑to‑pin logic delay on all pins.
How many macrocells does the XC95144 contain?
The device contains 144 macrocells providing up to 3,200 usable gates.