Xilinx XCR5128 CPLD Datasheet

Introduces the features and characteristics of Xilinx XPLA PLD, including TotalCMOS PLD, Fast Zero Power design technique, IEEE 1149.1-compliant, JTAG Testing Capability, 5V, In-System Programmable (ISP), high speed pin-to-pin delays, ultra-low static power, 100% routable, four clocks, programmable clock polarity, support for asynchronous clocking, innovative XPLA™ architecture, 1000 erase/program cycles, 20 years data retention, logic expandable to 37 product terms, PCI compliant, Advanced 0.5µ E2CMOS process, Security bit prevents unauthorized access, Design entry and verification using industry standard and Xilinx CAE tools, Reprogrammable using industry standard design tools


Xilinx XCR5128 CPLD Datasheet - cover page
Brand
Xilinx
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
20
File format
PDF
File size
119 KB
Published
07 June, 2012
Updated
30 September, 2023
MD5 checksum
C16F87D485CD05446678E2E8CA82DDEB

About this manual

The XCR5128 is a Complex Programmable Logic Device (CPLD) from the CoolRunner family by Xilinx. It utilizes the innovative XPLA architecture, combining high speed with extreme flexibility through a Zero-power Interconnect Array (ZIA). The device offers true pin-to-pin speeds of 7.5 ns and ultra-low static power of less than 100 µA at standby.

What's inside

  • Features
  • Description
  • XPLA Architecture
  • Logic Block Architecture
  • Macrocell Architecture

Frequently asked questions

What is the maximum number of product terms supported by the XCR5128?

The device supports logic expansion up to a total of 37 product terms.

What is the guaranteed pin-to-pin propagation delay for the XCR5128?

The worst-case pin-to-pin delay is 9.5 ns when using six to 37 product terms.

How many macrocells are included in the XCR5128 device?

The XCR5128 contains a total of 128 macrocells.

Download PDF (119 KB)

More Xilinx Manuals


View all Xilinx manuals →