This document is the Spartan™-3 FPGA data sheet from Xilinx, including introduction, functional description, electrical characteristics, timing characteristics and pinout descriptions.
The Spartan‑3 family of Field‑Programmable Gate Arrays is designed for high‑volume, cost‑sensitive consumer electronic applications. It offers densities from 50 K to 5 M system gates, a rich set of I/O standards, block RAM, dedicated multipliers and Digital Clock Manager blocks.
The document is organized into four modules: Introduction and Ordering Information, Functional Description, DC and Switching Characteristics, and Pinout Descriptions. It details configuration modes, power rails, I/O capabilities, and provides detailed pin‑out tables for each package type.
| Logic cells | 74,880 |
|---|---|
| Maximum system clock rate | 326 MHz |
| User I/O pins | 784 |
| Total block RAM | 1,872 Kbits |
| Dedicated multipliers | 18 × 18 |
Spartan‑3 devices can be configured using Master Parallel, Slave Parallel, Master Serial, Slave Serial, or Boundary Scan (JTAG) modes.
The family supports up to 784 user I/O pins.
Spartan‑3 FPGAs can operate at a system clock rate of up to 326 MHz.
They provide up to 1,872 Kbits of total block RAM and up to 520 Kbits of distributed RAM.