This document is about the product specifications of Xilinx's Spartan-3 FPGA, including introduction, features, architectural overview, array sizes and resources, user I/O chart, and ordering information.
This document is a complete data sheet for the Xilinx Spartan-3 Field-Programmable Gate Array (FPGA) family. It consolidates four separate modules into one volume to facilitate easy downloading and searching of the full specification.
The Spartan-3 family is designed for high-volume, cost-sensitive consumer electronic applications, offering densities ranging from 50,000 to five million system gates. Key features include SelectIO signaling with up to 784 I/O pins, dedicated 18x18 multipliers, Digital Clock Managers (DCM), and support for DDR SDRAM.
| Logic Cell Density Range | 50,000 to five million system gates |
|---|---|
| Maximum Logic Cells | 74,880 logic cells |
| Total I/O Pins | Up to 784 I/O pins |
| Data Transfer Rate per I/O | 622 Mb/s |
| Signal Standards Supported | 18 single-ended and 8 differential standards |
| Total Block RAM Capacity | Up to 1,872 Kbits |
The Spartan-3 family is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications.
The XC3S5000 device contains 74,880 logic cells.
Spartan-3 FPGAs support Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary Scan (JTAG) modes.