XC95108 is a high-performance CPLD from Altera that provides advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of six 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5ns.
The XC95108 is a high‑performance CPLD offering in‑system programmable (ISP) capability, 108 macrocells, up to 108 user I/O pins, and 7.5 ns pin‑to‑pin logic delays. It supports 5 V ISP, 10,000 program/erase cycles, and includes extensive JTAG boundary‑scan support.
The document lists absolute maximum ratings, recommended operating conditions, detailed DC and AC characteristics, internal timing parameters, I/O pin assignments, and ordering information for multiple package options such as 84‑pin PLCC and 100‑pin PQFP/TQFP.
| Pin‑to‑pin logic delay | 7.5 ns |
|---|---|
| Number of macrocells | 108 |
| User I/O pins | Up to 108 |
| Programming endurance | 10,000 program/erase cycles |
| Storage temperature range | -65 °C to +150 °C |
The device supports up to 10,000 program/erase cycles.
The XC95108 has a typical pin‑to‑pin logic delay of 7.5 ns.