The document is the specification of Xilinx's XC1700 series configuration PROM product, which introduces the product's features, characteristics, interfaces, packaging, and usage methods.
The XC1700 series configuration PROMs provide a simple, low‑cost solution for storing large Xilinx FPGA configuration bitstreams. They are one‑time programmable (OTP) read‑only memories with a single‑pin interface, programmable reset polarity, and can be cascaded to increase storage capacity. The devices are offered in 5 V and 3.3 V versions and in a variety of compact plastic packages such as 8‑pin SOIC, 20‑pin PLCC, and 44‑pin VQFP.
The PROMs connect directly to the FPGA: the FPGA’s CCLK drives the PROM’s CLK input, the PROM’s DATA output connects to the FPGA’s DIN pin, and the CEO output of one PROM can drive the CE input of the next PROM for daisy‑chaining. Reset polarity can be programmed as active‑High or active‑Low, and the devices support both Master Serial and Slave Serial configuration modes.