The MAX12554 is a 3.3V, 14-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The MAX12554 is optimized for high dynamic performance, low power, and small size. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12554 ideal for intermediate-frequency (IF) sampling applications. Powered from a single 3.3V supply, the MAX12554 consumes only 429mW while delivering a typical 70.9dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. In addition to low operating power, the MAX12554 features a 300µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX12554 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX12554 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12554 supports either a single-ended or differential input clock. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 14-bit, parallel, CMOS-compatible out
The MAX12554 is a 3.3 V, 14‑bit, 80 Msps analog‑to‑digital converter featuring a fully differential wideband track‑and‑hold input amplifier and a low‑noise internal quantizer. It supports single‑ended or differential inputs, an internal 2.048 V bandgap reference or an external reference, and offers CMOS‑compatible parallel outputs selectable as two’s‑complement or Gray code.
The device is supplied in a 6 mm × 6 mm × 0.8 mm, 40‑pin thin QFN package with exposed paddle, operates over an extended industrial temperature range (‑40 °C to +85 °C), and provides low power consumption (429 mW in differential‑clock mode, 300 µW power‑down). It is targeted at IF and baseband communication receivers, medical imaging, video imaging, and portable instrumentation applications.
| Resolution | 14 bits |
|---|---|
| Maximum Sampling Rate | 80 Msps |
| Supply Voltage | 3.3 V |
| Power Consumption (Differential Clock) | 429 mW |
| Full‑Scale Input Range | +0.35 V to +1.10 V |
| Package | 40‑Pin Thin QFN 6 mm × 6 mm × 0.8 mm |
| Operating Temperature Range | ‑40 °C to +85 °C |
| Signal‑to‑Noise Ratio (175 MHz) | 70.9 dB |
The maximum clock frequency is 80 MHz.
It consumes 429 mW in differential‑clock mode.
It is offered in a 40‑pin thin QFN package measuring 6 mm × 6 mm × 0.8 mm with an exposed paddle.
The input range can be set from +0.35 V to +1.10 V.