The document describes a 1.2 GHz Clock Distribution IC with PLL Core, Dividers, Delay Adjust, and Eight Outputs.
The AD9510 is a 1.2 GHz clock distribution IC that integrates a low‑phase‑noise PLL core, programmable dual‑modulus prescaler, and eight independent clock outputs. Four outputs are fixed LVPECL (1.2 GHz) and the other four can be configured as LVDS (800 MHz) or CMOS (250 MHz). The device offers fine‑delay adjustment, additive jitter as low as 225 fs rms for LVPECL and 275 fs rms for LVDS/CMOS, and a serial control port for programming.
The part operates from a single 3.3 V supply, with an optional separate charge‑pump supply (VCP) up to 5.5 V for extended VCO range. It is supplied in a 64‑lead LFCSP package and is rated for –40 °C to +85 °C. The datasheet provides detailed specifications, pin descriptions, timing diagrams, and application notes for high‑performance data‑converter clocking and other low‑jitter applications.
| Reference Input Frequency | 250 MHz |
|---|---|
| LVPECL Output Frequency | 1200 MHz |
| LVDS Output Frequency | 800 MHz |
| CMOS Output Frequency | 250 MHz |
| Supply Voltage (core) | 3.3 V |
| Charge‑Pump Supply Voltage (VCP) | 5.5 V max |
| Operating Temperature Range | –40 °C to +85 °C |
| Additive Output Jitter (LVPECL) | 225 fs rms |
| Additive Output Jitter (LVDS/CMOS) | 275 fs rms |
| Number of Independent Clock Outputs | 8 |
The reference inputs accept frequencies up to 250 MHz.
The AD9510 provides eight independent clock outputs: four fixed LVPECL outputs and four that can be selected as either LVDS or CMOS.