Industrial

This document describes the features and advantages of Wafer level chip scale packaging (WLCSP) technology, as well as manufacturing process optimization recommendations for Fairchild Semiconductor WLCSP components.

This paper discusses how to improve the power performance of the SuperSOTTM-6 Power MOSFET by optimizing the design of copper mounting pads. By using the thermal solution suggested in the document, users can take full advantage of the exceptional performance features of Fairchild Semiconductor's latest Power MOSFET, including very low on-resistance and improved junction-to-case thermal resistance (RθJC). This ultimately leads to improved component performance and higher circuit board packing density.

This design guide describes the design of asymmetric PWM half-bridge converters using Fairchild FSFA-series power switches (FPSTM) with a current doubler and synchronous rectifier.

This document introduces practical aspects of using PowerMOS transistors to drive inductive loads, including application scenarios, circuit principles, and characteristic analysis.

This application note describes a test method for testing the safe operating area of power MOS transistors without a heat sink. The method does not use a heat sink, but relies on the thermal capacitance (CT) of the package to allow prediction of the case temperature during SOA testing.

This document introduces the features and characteristics of Fairchild MicroFET™ package, including small size, low weight, thin base and good thermal and electrical performance.

This application note presents practical step-by-step design considerations for an interleaved Boundary-Conduction- Mode (BCM) Power-Factor-Correction (PFC) converter employing Fairchild PFC controllers FAN9611 and FAN9612. It includes designing the inductor and Zero- Current-Detection (ZCD) circuit, selecting the components, and closing the control loop. The design procedure is verified through an experimental 400W prototype converter. The FAN9611/12 interleaved dual BCM PFC controller operates two parallel-connected boost power trains 180º out of phase, extending the maximum practical power level of this control technique from 200-300W to greater than 800W. Unlike the Continuous Conduction Mode (CCM) technique often used at this power level, BCM offers inherent zero-current switching of the boost diodes (no reverse-recovery losses), which permits the use of less expensive diodes without sacrificing efficiency. Furthermore, the input and output filters can be made smaller due to ripple cancellation between the power stages and the effective doubling of the switching frequency. The advanced line feed-forward with peak detection circuit minimizes the output voltage variation during line transients. To guarantee stable operation with less switching loss at light load

This application note describes a 150W rating design guideline for LED street lighting. The application design consists of CRM PFC and LLC SRC with high power factor and high power conversion efficiency using FL7930B and FAN7621S.

This application note presents a LED application design guide using the FL7930 BCM Power-Factor-Correction (PFC) controller. It includes the design steps for inductor and Zero-Current-Detection (ZCD) circuit, component selection, and control loop closure. The FL7930 has additional features such as overvoltage protection and PFC-ready pin for triggering other power stages or synchronization with PFC voltage condition.

This application note presents a LED application design guide using BCM Power Factor Correction (PFC) controller for a 200W lighting system. The design procedure is verified through an experimental 200W prototype converter.

This application note discusses potential failure mode and mechanism in LLC resonant converters and provides a simple and cost-effective solution to prevent failures.

This article introduces the design guidelines for gate resistance (Rg) of SupreMOS® products in hard switch applications. By optimizing gate drive, higher power conversion efficiency can be achieved. The article also provides the minimum and maximum recommended values of Rg and offers tables for selecting Rg based on different conditions. Additionally, it discusses the considerations for switch losses when using SupreMOS products as replacements for other power MOSFETs.

This document provides gate resistor design guidelines for SupreMOS® MOSFETs. It discusses the minimum and maximum values of gate resistor to achieve optimal performance in hard-switching applications.

This application note discusses the advantages of planar technology power MOSFET in discontinuous current mode power factor correction application. In most test conditions, it is cost competitive and provides performance benefits compared to a super-junction technology device. The benefits are verified through mathematical simulation and system-level experiments. A new planar technology power MOSFET from Fairchild shows faster switching characteristics that contribute to higher efficiency and lower device temperature.

This document introduces the UIS rating system for PowerMOS transistors, which is used to evaluate whether the transistor can withstand the UIS stress level