This document provides information about Altera's HardCopy II devices, including their features and characteristics.
This handbook serves as a complete reference for the HardCopy II device family. It details the functional description, architecture, and features of these programmable logic devices, including HCells, embedded memory, PLLs, clock networks, and I/O structures. The document also covers boundary-scan support (IEEE Std 1149.1) and provides extensive DC and switching specifications.
The Quartus II software supports HardCopy II devices and includes features for planning and compiling designs.
Designers use the TimeQuest Timing Analyzer or the Classic Timing Analyzer to constrain and check timing.