Fairchild Semiconductor Dual Cool MOSFETs Application Note

Describes the package construction, thermal characterization challenges and some systemic examples utilizing heat sinks of Fairchild Semiconductor Dual CoolTM MOSFETs.


Fairchild Semiconductor Dual Cool MOSFETs Application Note - cover page
Brand
Fairchild
Category
Other Electronics
Document type
Application Note
Language
English
Pages
9
File format
PDF
File size
413 KB
Published
12 July, 2012
Updated
30 September, 2023
MD5 checksum
96C19CAFC1CA0BFE76424C4CEF329938

About this manual

This document details the Fairchild Semiconductor Dual Cool packaging technology, which features a heat slug on the top of the package to allow for supplemental cooling in addition to the standard drain-to-board conduction path. The note explains that this design uses 4 mils thin silicon to improve thermal and electrical performance compared to traditional 8 mil thick silicon dice.

The document addresses the challenges of thermal characterization for board designers, particularly when using infrared thermographs with heat sinks. It proposes a test methodology involving the attachment of a thermocouple to an unplated via in the drain pad to accurately measure junction temperatures. The text also includes experimental results comparing the thermal performance of Dual Cool, clip-bonded, and wire-bonded devices using different thermocouple sizes.

What's inside

  • Introduction
  • Package Construction
  • Challenge for Board Designers
  • Test Methodology
  • Thermocouple Size Experiment
  • Thermal Performance Without a Heat Sink Experiment

Frequently asked questions

What is the recommended thickness for a thermocouple used to measure Dual Cool device temperatures?

The document recommends using a 36 gauge thermocouple because it has less impact on the data and allows for a smaller drilled hole.

What diameter hole should be drilled in the drain pad to insert a thermocouple?

The verification boards used in the study had a 28 mils diameter hole drilled for the thermocouple.

What is the acceptable voiding percentage for the device when using a verification board?

Up to 25% voiding is considered acceptable and not problematic for the verification board.

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