The 74HC/HCT109 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together
The Philips 74HC/HCT109 is a high-speed Si-gate CMOS device featuring dual positive-edge triggered JK flip-flops with individual J, K, clock, set, and reset inputs. These devices are pin compatible with low power Schottky TTL (LSTTL) and comply with JEDEC standard no. 7A.
| Output capability | standard |
|---|---|
| Maximum clock frequency (HC) | 75 MHz |
| Input capacitance | 3.5 pF |
| Propagation delay (HCT) | 20 ns |
The device features dual positive-edge triggered JK flip-flops.
The set and reset inputs are asynchronous and active LOW.
Yes, by tying the J and K inputs together.