This document describes the features and characteristics of IDT's TeraSync DDR/SDR FIFO product, including different memory organizations and clock operation frequencies.
The IDT72T2098, IDT72T20108, IDT72T20118, and IDT72T20128 are exceptionally deep, extremely high-speed CMOS First-In-First-Out (FIFO) memories. These devices support the ability to read and write data on both rising and falling edges of the clock and offer flexible x20/x10 bus-matching modes. They provide user-selectable Single or Double Data Rate options for both input and output ports, making them suitable for network, video, and telecommunications applications requiring fast data transfer.
| Operation Frequency | Up to 250MHz |
|---|---|
| Access Time | 3.2ns |
| Data Rate | 500Mb/s |
| Package Type | 208 Ball Grid array (PBGA) |
| Package Dimensions | 17mm x 17mm |
| Technology | High-performance submicron CMOS |
| Temperature Range (Industrial) | -40°C to +85°C |
The available organizations are 32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10, 131,072 x 20/262,144 x 10, and 262,144 x 20/524,288 x 10.
The devices support 2.5V LVTTL or 1.8V, 1.5V HSTL selectable input/output voltage.
Yes, users can select Single or Double Data Rate for both input and output ports.