This is a datasheet for IDT72V223, IDT72V233, IDT72V243, IDT72V253, IDT72V263, IDT72V273, IDT72V283, IDT72V293.
The IDT SuperSync II FIFO family provides high‑density, low‑latency memory buffers with flexible 9‑bit or 18‑bit bus‑matching on both read and write ports. Devices support both synchronous and asynchronous operation, programmable flags, and optional zero‑latency retransmit.
Key features include 3.3 V supply, industrial temperature range, multiple package options (80‑pin TQFP or 100‑pin BGA), and up to 1 Mbit of storage capacity. The datasheet details pin functions, reset behavior, timing modes, and JTAG boundary‑scan support.
| Supply Voltage | 3.3 V |
|---|---|
| Operating Temperature Range | -40 °C to +85 °C |
| Package Options | 80‑pin TQFP or 100‑pin BGA |
| Maximum Storage Depth | up to 128 K × 9 bits (≈1 Mbit) |
| Maximum Clock Frequency | up to 166 MHz |
| Number of Flag Pins | 5 |
| Input Voltage Tolerance | 5 V tolerant inputs |
The device operates from a 3.3 V supply.
It is rated for industrial temperatures from –40 °C to +85 °C.
They are offered in an 80‑pin TQFP or a 100‑pin BGA package.
Each device provides five flag pins for status monitoring.