Key facts
- Brand
- IDT
- Model
- IDT72V223
- Industry
- Industrial
- Documents
- 2
- Languages
- EN
- Last added
- 2012-06-04
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IDT IDT72V223 IDT72V233 3.3 VOLT HIGH-DENSITY SUPERSYNC II
The IDT SuperSync II FIFO family provides high‑density, low‑latency memory buffers with flexible 9‑bit or 18‑bit bus‑matching on both read and write ports. Devices support both synchronous and asynchronous operation, programmable flags, and optional zero‑latency retransmit.
Key features include 3.3 V supply, industrial temperature range, multiple package options (80‑pin TQFP or 100‑pin BGA), and up to 1 Mbit of storage capacity. The datasheet details pin functions, reset behavior, timing modes, and JTAG boundary‑scan support.
IDT IDT72V223 specifications
| Supply Voltage | 3.3 V |
|---|---|
| Operating Temperature Range | -40 °C to +85 °C |
| Package Options | 80‑pin TQFP or 100‑pin BGA |
| Maximum Storage Depth | up to 128 K × 9 bits (≈1 Mbit) |
| Maximum Clock Frequency | up to 166 MHz |
| Number of Flag Pins | 5 |
| Input Voltage Tolerance | 5 V tolerant inputs |
Source: IDT IDT72V223 IDT72V233 3.3 VOLT HIGH-DENSITY SUPERSYNC II
All IDT IDT72V223 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What supply voltage is required for the IDT SuperSync II FIFO?
The device operates from a 3.3 V supply.
From: IDT IDT72V223 IDT72V233 3.3 VOLT HIGH-DENSITY SUPERSYNC II
What temperature range can the FIFO operate in?
It is rated for industrial temperatures from –40 °C to +85 °C.
From: IDT IDT72V223 IDT72V233 3.3 VOLT HIGH-DENSITY SUPERSYNC II
What does the Partial Reset (PRS) do?
Partial Reset initializes the read and write pointers to the first memory location while keeping the existing timing mode, programming method, and flag settings unchanged.
From: IDT IDT72V223 IDT72V233 IDT72V243 IDT72V253 IDT72V263 IDT72V273 IDT72V283 IDT72V293 handbook
How can the programmable flags be loaded?
Flags can be loaded serially using SEN and LD on each WCLK edge, or in parallel using WEN and LD on each WCLK edge.
From: IDT IDT72V223 IDT72V233 IDT72V243 IDT72V253 IDT72V263 IDT72V273 IDT72V283 IDT72V293 handbook