Update: 30 September, 2023
The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built using an advanced dual metal CMOS technology. They have eight edge-triggered, D-type flip-flops with individual D inputs and O outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s O output. The CE input must be stable only one set-up time prior to the LOW-to-HIGH transi- tion for predictable operation.
File format: PDF
Size: -
MD5 Checksum: F02A790D4D7A6521E55F55EFD43B1F2E
Publication date: 05 June, 2012
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PDF Link: IDT IDT54/74FCT377T/AT/CT/DT handbook(1) PDF