The SY10/100E154 is a 5-bit 2:1 multiplexer followed by latches with differential outputs, designed for use in new, high-performance ECL systems. It features asynchronous master reset, dual latch-enables, and is fully compatible with industry standard 10KH, 100K ECL levels. The product is available in a 28-pin PLCC package.
The SY10E154 and SY100E154 are 5‑bit 2:1 mux‑latch devices offered in a 28‑pin PLCC package. They provide differential outputs, asynchronous master reset, dual latch‑enable signals, and are compatible with standard ECL voltage levels.
The document includes pin‑out diagrams, truth tables, DC and AC electrical characteristics, ordering codes, and mechanical dimensions, allowing designers to integrate the parts into high‑performance ECL systems.
| Maximum Output Low Voltage (VEE) range | -4.2 V to -5.5 V |
|---|---|
| Reset Recovery Time (tRR) typical | 600 ps |
The SY10E154 is available with ordering codes SY10E154JC and SY10E154JCTR, both in a J28‑1 PLCC package.
The SY10E154 supports a VEE range from –4.2 V to –5.5 V.