The SY10/100E156 is a 3-bit 4:1 MUX-Latch designed for use in new, high-performance ECL systems. It features differential outputs, asynchronous Master Reset, dual latch enables, fully compatible with industry standard 10KH, 100K ECL levels, internal 75KΩ input pulldown resistors, and is available in a 28-pin PLCC package.
The SY10E156 and SY100E156 are 3‑bit 4:1 multiplexers with latch outputs designed for high‑performance ECL systems. They include dual latch enable signals, asynchronous master reset, and differential outputs. Pin functions and block diagrams are detailed for system integration.
Key specifications include propagation delays as low as 400 ps, typical supply currents around 75 mA, a VEE range of –4.2 V to –5.5 V, and availability in a 28‑pin PLCC package. Ordering codes and mechanical dimensions are also listed.
| Propagation Delay (tPHL) max | 900 ps |
|---|---|
| Propagation Delay (tPHL) typ | 600 ps |
| Input HIGH Current (I_IH) | 150 µA (typ) |
| VEE voltage range | -4.2 V to -5.5 V |
| Package | 28‑pin PLCC |
| Ordering code (SY10E156) | SY10E156JC |
Typical propagation delay (tPHL) is 600 ps and the maximum is 900 ps.
The device has two latch enable signals (LEN1 and LEN2) that are OR‑gated; when both are low the latches are transparent, otherwise the outputs are latched.
It is available in a 28‑pin PLCC package.
The VEE range is –4.2 V to –5.5 V.