The SY10E195/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the E195 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent. Because the delay programmability of the E195 is achieved by purely differential ECL gate delays, the device will operate at frequencies of >1GHz, while maintaining high push-pull outputs, suitable for a wide variety of circuit applications.
The SY10E195 and SY100E195 are Micrel programmable delay chips (PDCs) intended for clock de‑skewing and timing adjustment. They provide up to 2 ns of delay with a 20 ps digital step resolution and support frequencies above 1 GHz.
The devices feature a 7‑bit address bus (D0‑D6) for selecting delay steps and an additional D7 pin for cascading multiple chips, allowing extended programmable range with only one extra address line per added device.