The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications.
The SY10E196 and SY100E196 are programmable delay chips designed for precise differential ECL input edge placement. They feature a linear analog FTUNE input that refines the 20 ps digital step resolution and provide a programmable range of up to 2 ns.
The devices are supplied in a 28‑pin PLCC package, operate with a VEE range of –4.2 V to –5.5 V, and include on‑chip cascade circuitry for extending the delay range without external gating. Electrical characteristics such as input pulldown resistance (75 kΩ) and bandwidth (>1 GHz) are also specified.
| Maximum programmable delay | 2 ns |
|---|---|
| Analog input voltage range (VEE) | –4.2 V to –5.5 V |
| Digital step resolution | ≈20 ps |
| Bandwidth | >1 GHz |
| Input pulldown resistor | 75 kΩ |
| Package | 28‑pin PLCC |
The analog input voltage (VEE) range is –4.2 V to –5.5 V.
The chips provide an approximate 20 ps digital step resolution.
Up to 2 ns of programmable delay is available.
Both devices are offered in a 28‑pin PLCC package.