The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity) and using ODDPAR as the byte parity output. The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level.
The SY10E175 and SY100E175 are 9‑bit latches with an odd‑parity output (ODDPAR). They latch nine data inputs and generate a parity signal that is HIGH when an odd number of inputs are HIGH. The devices are fully compatible with Motorola MC10E/100E175 logic families and are offered in a 28‑pin PLCC package.
Key specifications include a D‑to‑Q propagation delay of up to 800 ps, input HIGH current of 150 µA minimum, and an operating voltage range of –4.2 V to –5.5 V. Ordering codes such as SY10E175JC and SY100E175JC identify the commercial package version.
| Input HIGH Current | 150 µA min |
|---|---|
| Power Supply Current (SY10E) | 110 mA typ |
| Propagation Delay D‑to‑Q | 800 ps max |
| Propagation Delay D‑to‑ODDPAR | 1450 ps max |
| Within‑Device Skew | 1 ps |
| Package | 28‑pin PLCC |
ODDPAR is HIGH when an odd number of the nine data inputs are HIGH, providing odd‑parity detection.
The maximum D‑to‑Q propagation delay is 800 ps.
They are offered in a 28‑pin PLCC package.