The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems.
The handbook describes the SY10E151 and SY100E151 high‑speed, edge‑triggered D‑type flip‑flops with differential outputs, their dual clock inputs, asynchronous master reset, and compatibility with standard ECL levels. It includes pin assignments, truth tables for asynchronous and synchronous operation, and detailed DC and AC electrical specifications.
Package information, ordering codes, and mechanical dimensions for the 28‑lead PLCC (J28) version are also provided, along with a disclaimer from Micrel.
| Toggle Frequency (max) | 1100 MHz |
|---|---|
| Input HIGH Current | 150 µA |
| Set‑up Time (D) | -175 ps |
| Hold Time (D) | 175 ps |
| Reset Recovery Time (min) | 550 ps |
| Minimum Pulse Width | 400 ps |
| Package Type | 28‑lead PLCC (J28) |
| Ordering Code (SY10E151) | JC J28‑1 Commercial |
The maximum toggle frequency is 1100 MHz.
They are offered in a 28‑lead PLCC (J28) package.
The devices have two clock inputs named CLK1 and CLK2.
The MR signal asynchronously forces all Q outputs to a logic LOW.