The MAX9174/MAX9175 are 670MHz, low-jitter, low-skew 1:2 splitters ideal for protection switching, loop- back, and clock and signal distribution. The devices feature ultra-low 1.0ps(RMS) random jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing errors. The MAX9174 has a fail-safe LVDS input and LVDS out- puts. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs. The MAX9174 features a fail-safe circuit that dri- ves the outputs high when the input is open, undriven and shorted, or undriven and terminated. The MAX9175 has a bias circuit that forces the outputs high when the input is open. The power-down inputs are compatible with standard LVTTL/LVCMOS logic. The power-down inputs tolerate undershoot of -1V and overshoot of VCC + 1V. The MAX9174/MAX9175 are available in 10-pin µMAX and 10-lead thin QFN with exposed pad pack- ages, and operate from a single +3.3V supply over the -40°C to +85°C temperature range.
The MAX9174 and MAX9175 are 670 MHz, low‑jitter, low‑skew 1:2 splitters designed for protection switching, loop‑back, and clock/signal distribution. MAX9174 provides a fail‑safe LVDS input, while MAX9175 accepts any differential input (CML/LVDS/LVPECL). Both devices feature power‑down inputs compatible with LVTTL/LVCMOS logic and operate from a single +3.3 V supply.
The datasheet details absolute maximum ratings, DC and AC electrical characteristics, typical operating curves, pin descriptions, and layout recommendations. It also includes ESD protection specifications (IEC 61000‑4‑2 Level 4) and package drawings for the 10‑pin µMAX and 10‑lead thin QFN options.
| Random Jitter (RMS) | 1.0 ps |
|---|---|
| Power Supply | +3.3 V |
| Operating Temperature Range | -40 °C to +85 °C |
| Package Types | 10‑pin µMAX, 10‑lead thin QFN |
| Input Types | LVDS fail‑safe (MAX9174), CML/LVDS/LVPECL (MAX9175) |
| Power‑Down Input Tolerance | -1 V undershoot, VCC + 1 V overshoot |
The devices have an ultra‑low random jitter of 1.0 ps RMS (maximum).
Both devices operate from a single +3.3 V supply.
They are offered in 10‑pin µMAX and 10‑lead thin QFN packages.
When the LVDS input is open, undriven and shorted, or undriven and terminated, an internal resistor pulls the input high, forcing the outputs high.