MAX9322 is a low-jitter 1:15 differential clock driver that reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from one of two input clocks with input switching frequency in excess of 1.0GHz. The 15 outputs are arranged in four banks with 2, 3, 4, and 6 outputs, respectively. Each output bank is individually programmable to provide a divide-by-1 or divide-by-2 frequency function. The MAX9322 operates in LVPECL systems with a +2.375V to +3.8V supply or in LVECL systems with a -2.375V to -3.8V supply. A VBB reference output provides compatibility with single-ended clock input signals and a master reset input provides a simultaneous reset on all outputs. The MAX9322 is available in 52-pin TQFP and 68-pin QFN packages and is specified for operation over -40°C to +85°C. For 1:10 clock drivers, refer to the MAX9311/MAX9313 data sheet. For 1:5 clock drivers, refer to the MAX9316 data sheet. Applications include precision clock distribution, low-jitter data repeaters, central-office backplane clock distribution, DSLAM backplane, base stations and ATE.
The MAX9322 is a low‑skew 1:15 differential clock driver that can reproduce or divide one of two differential input clocks up to 1.0 GHz. It offers 15 differential outputs arranged in four banks with selectable divide‑by‑1 or divide‑by‑2 functionality and includes a master reset and compatibility with single‑ended clock inputs.
The device is offered in 52‑pin TQFP and 68‑pin QFN packages and operates over a temperature range of –40 °C to +85 °C. Detailed pin functions, electrical characteristics, and package dimensions are provided for designers.
| Supply Voltage (VEE) | -2.375 V to -3.8 V |
|---|---|
| Supply Voltage (VCC) | +2.375 V to +3.8 V |
| Number of Differential Outputs | 15 |
| Package Types | 52‑pin TQFP, 68‑pin QFN |
| ESD Protection (Human Body Model) | >2 kV |
| Output Jitter (RMS) | 1.2 ps |
It provides 15 differential outputs arranged in four banks.
It is rated for greater than 2 kV Human Body Model protection.