Cypress CY7C132 Dual-Port SRAM Datasheet

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Cypress CY7C132 Dual-Port SRAM Datasheet - cover page
Brand
Cypress
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
18
File format
PDF
File size
727 KB
Published
05 May, 2012
Updated
30 September, 2023
Model
CY7C132
MD5 checksum
8EB812526F58C480447F69AEE5038AEF

About this manual

The CY7C132 is a high‑speed 2 K × 8 dual‑port static RAM offering true dual‑ported memory cells for simultaneous reads. It operates with a 0.65‑µm CMOS process, providing 15 ns access time and low power consumption (Ioc = 110 mA max). The device can function as a standalone 8‑bit RAM or as a master in a 16‑bit configuration when paired with the CY7C142 slave.

The datasheet includes detailed pin configurations for DIP, PLCC and TQFP packages, electrical characteristics over a wide voltage and temperature range, and timing diagrams for read/write cycles, BUSY and interrupt signals. Package diagrams and selection guides help designers choose the appropriate variant for their application.

What's inside

  • Features
  • Functional Description
  • Pin Configuration
  • Electrical Characteristics
  • Switching Characteristics
  • Timing Diagrams
  • Package Diagrams
  • Selection Guide
  • Maximum Ratings

Specifications

Memory organization2K × 8
Access time15 ns
Operating temperature (industrial)-40 °C to +85 °C
Maximum operating current110 mA (max)

Frequently asked questions

What package options are available for the CY7C132?

The CY7C132 is offered in 48‑pin DIP, 52‑pin PLCC and 52‑pin TQFP packages.

Does the CY7C132 have a power‑down feature?

Yes, the device includes an automatic power‑down function controlled by the chip‑enable pins.

What is the purpose of the BUSY pin on the CY7C132?

The BUSY pin provides an output flag indicating the port is trying to access a location currently used by the other port.

What is the maximum access time for the 15‑ns version?

The 15‑ns version offers a maximum access time of 15 ns.

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