The product is a 4-Mbit (128K x 32) Pipelined Sync SRAM with registered inputs and outputs for pipelined operation, 128K × 32 common I/O architecture, 3.3V core power supply, 2.5V / 3.3V I/O operation, fast clock-to-output times (250-MHz device for 2.6 ns, 225-MHz device for 2.6 ns, 200-MHz device for 2.8 ns, 166-MHz device for 3.5 ns, 133-MHz device for 4.0 ns, 100-MHz device for 4.5 ns), provides high-performance 3-1-1-1 access rate, user-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences, separate processor and controller address strobes, synchronous self-timed writes, asynchronous output enable, offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages, and “ZZ” Sleep Mode Option.
This document describes the Cypress CY7C1339F 4‑Mbit (128K × 32) pipelined synchronous SRAM. It includes features such as registered inputs/outputs, 3.3 V core supply, 2.5 V/3.3 V I/O operation, and fast clock‑to‑output times for speeds up to 250 MHz.
The datasheet contains detailed pin configurations for both 100‑pin TQFP and 119‑ball BGA packages, functional block diagrams, burst‑mode operation (interleaved and linear), maximum ratings, and electrical characteristics across the operating temperature range.
| Memory size | 4‑Mbit (128K × 32) |
|---|---|
| Core supply voltage | 3.3 V |
| I/O supply voltage | 2.5 V or 3.3 V |
| Maximum access time (250 MHz) | 2.6 ns |
| Maximum operating current (250 MHz) | 325 mA |
| Power supply voltage (Vop) | 3.135 V–3.6 V |
The device uses a 3.3 V core power supply.
The maximum access time is 2.6 ns.
It is offered in JEDEC‑standard 100‑pin TQFP and 119‑ball BGA packages.