Update: 01 October, 2023
The product is a 4-Mbit (128K x 32) Pipelined Sync SRAM with registered inputs and outputs for pipelined operation, 128K × 32 common I/O architecture, 3.3V core power supply, 2.5V / 3.3V I/O operation, fast clock-to-output times (250-MHz device for 2.6 ns, 225-MHz device for 2.6 ns, 200-MHz device for 2.8 ns, 166-MHz device for 3.5 ns, 133-MHz device for 4.0 ns, 100-MHz device for 4.5 ns), provides high-performance 3-1-1-1 access rate, user-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences, separate processor and controller address strobes, synchronous self-timed writes, asynchronous output enable, offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages, and “ZZ” Sleep Mode Option.
File format: PDF
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MD5 Checksum: AB5CAEFACB743D78CF69901F3748F202
Publication date: 07 May, 2012
Downloads: -
PDF Link: CYPRESS CY7C1339F Manual PDF