This document introduces the AD9540 low jitter clock generator
The AD9540 clock generator from Analog Devices is designed for high‑performance data converters and demanding clocking applications such as base‑station, SONET/SDH, Gigabit Ethernet and automotive radar. It features a 200 MHz phase‑frequency detector, programmable charge‑pump, and a 655 MHz CML‑mode PECL‑compliant output driver with programmable slew rates.
The device operates over an extended automotive temperature range (‑40 °C to +85 °C) and supports external VCOs up to 2.7 GHz. Power consumption is low (400 mW total) and it offers a serial I/O port with a 25 Mbps write speed for configuration.
| Total system jitter (105 MHz ADC clock) | 720 fs rms |
|---|---|
| Phase noise @ 10 Hz offset | 80 dBc/Hz |
| Supply voltage (AVDD/DVDD) | 18 V ±5% |
| Total power consumption (all functions on) | 400 mW |
| Operating temperature range | ‑40 °C to +85 °C |
| Output driver type | 655 MHz CML‑mode PECL‑compliant |
| Input voltage levels (P‑P) | 200 mV – 600 mV |
The AD9540 is specified to operate over the extended automotive range of –40 °C to +85 °C.
Total power consumption with all functions on is 400 mW.
The converter limiting jitter is 720 fs rms.
It provides a 655 MHz CML‑mode PECL‑compliant output driver.