The ADN4670 is a low‑voltage differential signaling (LVDS) clock driver that distributes a single differential clock input to ten LVDS clock outputs. It features selectable input sources, individual output enable/disable, and fail‑safe operation during power‑down.
The device operates from a 2.375 V to 2.625 V supply, supports up to 1.1 GHz input clock rates, and offers typical output skew under 30 ps. It is offered in 32‑lead LFCSP and LQFP packages and meets industrial temperature specifications (‑40 °C to +85 °C).
| Supply Voltage (VDD) | 2.375 V to 2.625 V |
|---|---|
| Low Output Skew | <30 ps (typical) |
| Maximum Input Clock Frequency | 900 MHz to 1100 MHz |
| Propagation Delay (Low‑to‑High) | 2 ns to 3 ns |
| Output Rise Time (tr) | 350 ps |
The device operates from 2.375 V to 2.625 V.
It provides ten differential LVDS clock outputs.
The maximum input frequency is between 900 MHz and 1100 MHz.
Typical output skew is less than 30 ps.