The AD9572 is a fiber channel/Ethernet clock generator IC with 7 clock outputs. The AD9572 uses a fully integrated dual VCO/PLL core, an input crystal or clock frequency of 25 MHz, preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz, 100 MHz and 125 MHz, a choice of LVPECL or LVDS output format, integrated loop filters, a copy of the reference clock output, rates configured via strapping pins, 3.3 V operation and a 6 mm × 6 mm, 40-lead LFCSP package.
The AD9572 provides a multi‑output clock generator function with two on‑chip PLL cores, optimized for fiber‑channel line‑card applications that include an Ethernet interface. It supports a variety of output frequencies (25 MHz – 156.25 MHz) and selectable LVPECL or LVDS output formats, making it suitable for high‑speed communication systems.
Key features include a compact 6 mm × 6 mm 40‑lead LFCSP package, 3.3 V supply operation, low power dissipation (0.71 W LVDS, 1.07 W LVPECL), and very low jitter (as low as 0.19 ps rms). The device operates from –40 °C to +85 °C and includes integrated loop filters, eliminating the need for external components.
| Supply Voltage (V_S) | 3.3 V (typ) |
|---|---|
| LVDS Power Dissipation | 0.71 W |
| LVPECL Power Dissipation | 1.07 W |
| Typical LVDS Jitter (106.25 MHz) | 0.22 ps rms |
| Package | 40‑lead 6 mm × 6 mm LFCSP |
| Operating Temperature Range | ‑40 °C to +85 °C |
| Number of Clock Outputs | 7 |
The device operates from a 3.3 V supply (typical), with a permissible range of 3.0 V to 3.6 V.
The AD9572 provides seven clock outputs, selectable for various frequencies and formats.
Typical jitter is 0.22 ps rms for the 106.25 MHz LVDS output.
It is offered in a 40‑lead, 6 mm × 6 mm lead‑frame chip‑scale package (LFCSP).