The SPP3401 is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits, and low in-line power loss are needed in a very small outline surface mount package.
The SPP3401 is a P‑Channel logic enhancement mode MOSFET designed for low‑voltage power management in notebook computers, cellular phones, and other battery‑powered circuits. It uses a high‑density DMOS trench process to achieve very low on‑state resistance and compact SOT‑23‑3L packaging.
The datasheet provides absolute maximum ratings, electrical characteristics, typical transfer curves, and package dimensions, along with ordering information and a legal disclaimer from SYNC Power Corporation.
| Drain‑Source Voltage (V_DSS) | -30 V |
|---|---|
| Gate‑Source Voltage (V_GS) | +12 V |
| Continuous Drain Current (I_D) | -4.0 A |
| On‑Resistance (R_DS(on)) typical | 0.055 Ω |
| Power Dissipation (P_D) | 0.8 W |
| Thermal Resistance Junction‑to‑Ambient (RθJA) | 120 °C/W |
| Package | SOT‑23‑3L |
The SPP3401 is rated for a maximum drain‑source voltage of -30 V.
It is supplied in a SOT‑23‑3L surface‑mount package.
The device can handle a continuous drain current of -4.0 A at 25 °C.