SPP3403 is a P-Channel logic enhancement mode power field effect transistor produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
The SPP3403 is a P‑Channel logic enhancement mode power MOSFET built with a high‑density DMOS trench process to achieve very low on‑state resistance. It is intended for low‑voltage applications such as notebook power management, battery‑powered systems, DC/DC converters, load switches, and LCD inverter circuits.
The datasheet lists absolute maximum ratings, detailed electrical characteristics, typical performance curves, and the SOT‑23‑3L surface‑mount package dimensions. It also includes ordering information and pin descriptions for designers.
| Drain‑Source Voltage (Vdss) | -30 V |
|---|---|
| Gate‑Source Voltage (Vgss) | +12 V |
| Continuous Drain Current (Id) at 150 °C | -2.8 A |
| On‑Resistance (RDS(on)) typical | 0.080 Ω |
The SPP3403 can tolerate a maximum drain‑source voltage of –30 V.