The SPP3403 is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
The SPP3403 is a P‑Channel logic enhancement mode power MOSFET built with high‑density DMOS trench technology, optimized for low on‑state resistance. It is intended for low‑voltage power‑management applications such as notebook computers, portable equipment, battery‑powered systems, DC/DC converters, load switches and LCD inverter circuits.
The document lists the pin configuration (SOT‑23‑3L package), ordering information, absolute maximum ratings, detailed electrical characteristics, typical performance curves and the mechanical dimensions of the package. Legal and warranty notices are included on the final page.
| Drain‑Source Voltage (Vdss) | -30 V |
|---|---|
| Gate‑Source Voltage (Vgss) | +12 V |
| On‑State Drain Current (Id) typical | 2.8 A (Vgs = -10 V) |
| On‑Resistance (RDS(on)) typical | 0.080 Ω |
The maximum drain‑source voltage is -30 V.