The 128‑Mb SDRAM family from Micron includes three configurations: 32 M × 4, 16 M × 8 and 8 M × 16 organized as quad‑bank DRAMs that operate at 3.3 V with a fully synchronous interface. Each bank contains 4,096 rows and a column depth that varies with the data width (2,048 columns for x4, 1,024 for x8, 512 for x16).
Key features include programmable burst lengths (1, 2, 4, 8 or full page), auto‑precharge, self‑refresh (64 ms, 4,096‑cycle), LVTTL‑compatible I/Os, and support for PC66/100/133 memory timings. The document provides functional block diagrams, pin descriptions, timing parameters, and detailed command definitions for proper initialization and operation.
| Organization | 32 M × 4, 16 M × 8, 8 M × 16 (quad‑bank) |
|---|---|
| Supply Voltage | +3.3 V ±0.3 V |
| Operating Temperature (Commercial) | 0 °C to +70 °C |
| Operating Temperature (Extended) | -40 °C to +85 °C |
| Package | 54‑pin TSOP (400 mil) TG |
| Burst Length Options | 1, 2, 4, 8 or full page |
| Self‑Refresh Interval | 64 ms (4,096 cycles) |
| Typical CL2 Timing | 10 ns @ CL2 (PC100) |
It operates from a single +3.3 V supply with a ±0.3 V tolerance.
Burst lengths of 1, 2, 4, 8 or a full‑page burst can be programmed.
The devices are rated for 0 °C to +70 °C in commercial applications.
The SDRAM is supplied in a 54‑pin TSOP (400 mil) package.