This application note describes how to implement a 267-MHz DDR2 controller in a Virtex™-4 device and interface it with a Micron DDR2 SDRAM device.
The document explains how to realize a 267‑MHz DDR2 controller inside a Virtex‑4 device and connect it to Micron DDR2 SDRAM. It covers the DDR2 SDRAM features, the controller operation, and the user‑backend interface.
Detailed sections describe the DDR2 command set, mode registers, initialization sequence, signal timing, and the design hierarchy of the reference implementation. Revision history and resource utilization are also provided. This manual is written in Chinese.
| Controller frequency | 267 MHz |
|---|---|
| Maximum DDR2 data rate | 400 Mb/s or higher |
| I/O standard | SSTL 1.8 V |
| Burst length options | 4 or 8 |
| CAS latency | 3 |
The sequence starts with CKE high, then PRECHARGE ALL, followed by EMR2, EMR3, EMR (DLL enable), MRS (DLL reset), another PRECHARGE ALL, two AUTO REFRESH commands, a final MRS without DLL reset, and optional OCD calibration.
Signals such as Af_addr, Af_empty, ctrl_af_RdEn, ctrl_wdf_RdEn, and others listed in Table 4 provide address, data, and control information between the user backend and the DDR2 controller.