The guide introduces the Initiator/Target v3.1 for PCI IP core, covering licensing, system requirements, and available resources. It explains how to obtain the core, install licensing files, and access additional documentation on Xilinx’s website.
Subsequent chapters detail design considerations for Virtex and Spartan devices, functional simulation with Cadence IUS and ModelSim, synthesis using Synplify, Leonardo Spectrum, and XST, and implementation steps in the ISE Foundation environment. The document also provides command‑line examples, script adjustments, and troubleshooting tips for successful bitstream generation.
| Supported FPGA families | Virtex and Spartan |
|---|---|
| PCI bus frequency | 66 MHz |
| Example target device | V300BG432-6 |
| Input buffer voltage compatibility | 3.3 V |
| Output driver VCC0 generation | 3.0 V |
The core supports 32‑bit and 64‑bit implementations for Virtex and Spartan architectures.
Functional simulation can be performed with Cadence IUS and Mentor Graphics ModelSim.
Set the Frequency parameter to 66 MHz in the Options/Constraints tab.