This application note will illustrate the new features of the LPC11U6x device family compared to the LPC11U3x device family.
This document serves as a feature comparison between the NXP LPC11U6x and LPC11U3x device families. It details the architectural differences, such as the upgrade from ARM Cortex-M0 to M0+ for the LPC11U6x, which includes features like a two-stage pipeline and single-cycle multiplier.
The note covers various hardware enhancements in the LPC11U6x series, including increased memory sizes (up to 256 kB Flash), expanded I/O capabilities with glitch-free pads, improved USB circuit design for reduced BOM costs, and new peripherals such as State Configurable Timers (SCT) and a CRC engine.
| Processor Architecture (LPC11U6x) | ARM Cortex-M0+ |
|---|---|
| Flash Memory (LPC11U3x) | up to 128 kB |
| Flash Memory (LPC11U6x) | up to 256 kB |
| Operating Temperature (LPC11U3x) | -40 °C to +85 °C |
| Operating Temperature (LPC11U6x) | -40 °C to +105 °C |
| ADC Resolution (LPC11U3x) | 10-bit |
| ADC Resolution (LPC11U6x) | 12-bit |
The LPC11U3x uses an ARM Cortex-M0, while the LPC11U6x uses an ARM Cortex-M0+ with a two-stage pipeline.
Yes, the LPC11U6x includes a Cyclic Redundancy Check (CRC) engine supporting CRC-CCITT, CRC-16, and CRC-32.
The LPC11U6x contains two I2C interfaces, whereas the LPC11U3x contains only one.