Key facts
- Brand
- IDT
- Model
- IDT23S09
- Category
- Other Electronics
- Documents
- 2
- Languages
- EN
- Last added
- 2012-06-15
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IDT IDT23S09 3.3V Zero Delay Clock Buffer Datasheet
Datasheet 8 pages · 54 KB · EN
The IDT IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer designed for high-speed clock distribution applications. It accepts one reference input and drives two banks of four low skew outputs, achieving zero delay by aligning the phase between incoming and output clocks within the range of 10 to 133MHz.
Read onlineIDT IDT23S09 specifications
| Operating Frequency Range | 10MHz to 133MHz |
|---|---|
| Supply Voltage | 3.3V VDD |
| Output Skew | < 250ps |
| Cycle-to-Cycle Jitter | < 200 ps |
| Operating Temperature (Industrial) | -40 to +85 °C |
All IDT IDT23S09 documents by type
Datasheet 2
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the maximum operating frequency of the IDT23S09?
The device operates at frequencies up to 133MHz.
Does the IDT23S09 require external RC networks for operation?
No, it does not require any external RC network.
What is the operating frequency range of the IDT23S09E?
The device operates within a frequency range of 10MHz to 200MHz.
Is the IDT23S09E spread spectrum compatible?
Yes, the product is designed to be spread spectrum compatible and does not filter off the feature of the reference input.