Key facts
- Brand
- IDT
- Model
- IDT71V3558SA
- Industry
- Industrial
- Documents
- 2
- Languages
- EN
- Last added
- 2012-06-07
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IDT IDT71V3558SA 3.3V Synchronous SRAM Datasheet
This document describes the IDT71V3556/58 family of 3.3V high-speed synchronous SRAMs available in 128K x 36 and 256K x 18 configurations. The devices utilize a Zero Bus Turnaround (ZBT) feature to eliminate dead cycles between read and write operations, supporting system speeds up to 200 MHz.
Read onlineIDT IDT71V3558SA specifications
| Memory Configurations | 128K x 36, 256K x 18 |
|---|---|
| Maximum System Speed | 200 MHz |
| Clock-to-Data Access Time | 3.2 ns |
| Supply Voltage (VDD) | 3.3V (+/- 5%) |
| Package Types | 100-pin TQFP, 119-ball BGA, 165-ball fBGA |
All IDT IDT71V3558SA documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the ZBT feature?
ZBT stands for Zero Bus Turnaround and eliminates dead cycles between write and read cycles.
How many chip enables does the device have?
The device has three chip enable pins (CE1, CE2, CE3) for simple depth expansion.
What does the ZBT feature mean?
ZBT (Zero Bus Turnaround) eliminates dead cycles between write and read operations, allowing continuous data flow.
From: IDT IDT71V3556S/IDT71V3558S/IDT71V3556SA/IDT71V3558SA handbook
How many chip‑enable pins does the device have?
The SRAM has three chip‑enable pins: CE1, CE2, and a second CE2 pin.
From: IDT IDT71V3556S/IDT71V3558S/IDT71V3556SA/IDT71V3558SA handbook