This guide details configuration schemes, design guidelines, and IP core implementation for MAX 10 FPGA devices using JTAG and internal configuration.
This document provides comprehensive information on configuring MAX 10 FPGA configuration RAM (CRAM) using JTAG or internal configuration schemes. It covers supported features such as remote system upgrades, design security, SEU mitigation, and data compression. The guide explains the differences between JTAG and internal configuration modes, including supported compression types and flash memory sectors for various device models.
| Supported Configuration Schemes | JTAG configuration and Internal configuration |
|---|---|
| Supported Features for JTAG | SEU Mitigation |
| Supported Features for Internal | Remote System Upgrade, Compression, Design Security, SEU Mitigation |
| CFM Sectors (10M04 and above) | Three sectors: CFM0, CFM1, and CFM2 |
| CFM Sectors (10M02) | One sector: CFM0 |
| Programming Time CFM0 (10M02) | 5.4 seconds |
| Programming Time CFM0 (10M40/50) | 52.9 seconds |
| JTAG Pin Standards | LVTTL/ LVCMOS 3.3-1.5V |
MAX 10 devices support JTAG configuration using the JTAG interface and internal configuration using internal flash.
No, JTAG configuration does not support Remote System Upgrade, Compression, Design Security, or SEU Mitigation.
The programming time for CFM0 in a 10M40 device is 52.9 seconds.