This document describes the high-speed differential interfaces in Cyclone II devices, including LVDS, RSDS, and mini-LVDS interfaces.
This document describes the high‑speed differential I/O capabilities of Altera Cyclone II FPGA devices. It covers LVDS, RSDS, mini‑LVDS, LVPECL, differential HSTL and differential SSTL standards, providing electrical specifications, pin‑bank information, and design guidelines for implementing these interfaces.
Design recommendations include trace routing, termination placement, resistor network configurations for RSDS, and PCB layout best practices to maintain signal integrity at data rates up to 805 Mbps for LVDS receivers and 640 Mbps for transmitters.
| LVDS input differential voltage (Vio) min‑typ | 0.1 V – 0.65 V |
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The LVDS transmitter supports data rates up to 640 Mbps.
A 100 Ω resistor is recommended for the RSDS external resistor (Rp).