The MPC8360E PowerQUICC II Pro integrated communications processor family is the next generation of the popular PowerQUICC II, built on Power Architecture technology. The series combines the next generation communications engine QUICC Engine, supporting a variety of different protocols including Gigabit Ethernet and QC-12 Asynchronous Transfer Mode (ATM)/Packet over Sonet (POS). Other enhancements include the e300 core, built on Power Architecture technology (enhanced version of the 603e core with larger cache capacity), clocked up to 667 MHz, 2 DDR memory controllers and an integrated security engine.
The Freescale MPC8360E PowerQUICC II Pro is a high‑performance, low‑power communication processor built on the e300 Power Architecture core. It integrates a QUICC Engine, dual DDR memory controllers, and a security engine supporting multiple encryption algorithms, targeting broadband access, wireless base stations, and SME routers.
The device offers extensive connectivity options, including up to eight Gigabit Ethernet ports, ATM, POS, TDM, USB 2.0, PCI, dual UART, dual I2C, SPI, and a rich set of UCC interfaces. Detailed technical specifications cover core frequencies, cache sizes, memory interfaces, and supported protocols. This manual is written in Chinese.
| Core frequency range | 266 MHz – 667 MHz |
|---|---|
| Maximum MIPS | 1261 MIPS at 667 MHz |
| Cache size | 32 KB data cache, 32 KB instruction cache |
| Ethernet interfaces | Up to 8×10/100/1000 Mbps ports |
| Security engine algorithms | DES, 3DES, MD‑5, SHA‑1, AES, ARC‑4 |
| Package | 740 TBGA (37.5 mm × 37.5 mm) |
It supports DES, 3DES, MD‑5, SHA‑1, AES and ARC‑4.
The processor includes dual UART (DUART) ports.
The core can run up to 667 MHz.
It is offered in a 740 TBGA package measuring 37.5 mm × 37.5 mm.