This document lists the upcoming features of the Stratix V device family from Altera Corporation. These features are not enabled in Quartus II software version 12.0, but will be supported in a future release of the software.
This manual details future support capabilities for the Stratix V device family within the Quartus II software environment. It outlines specific enhancements scheduled for a future release, covering configuration protocols, FPGA fabric features, and external memory interfaces.
The document is organized by feature category, including partial reconfiguration, Unique ID implementation, and Single Event Upset (SEU) mitigation. It also provides tables listing supported transceiver standards such as PCIe Gen1/Gen2/Gen3 and 10G PCS protocols, along with clocking features like fractional PLLs and dynamic phase shift.
| Software Version Context | Quartus II software version 12.0 |
|---|---|
| DDR3 Frequency Support | up to 1,066 MHz |
The features listed are not currently enabled in Quartus II software version 12.0.
Yes, users will be able to partially reconfigure Stratix V devices while the rest of the device is still operating.