Altera Arria GX Device Family Pin Connection Guidelines

About this manual

The Arria® GX Device Family Pin Connection Guidelines (PCG-01002-1.1) serve as a recommendation rather than a formal specification for connecting pins on Altera programmable logic devices. Users are advised to verify device operation against the official datasheet before relying on these guidelines for design implementation.

The document outlines specific connection requirements for various pin types, including supply and reference pins (such as VCCINT, VCCIO, and VCCPD) with their respective voltage levels and decoupling needs. It also covers dedicated configuration STAG pins like nI/O_Pullup and VCCSEL, explaining how to set logic levels to control internal pull-ups and select input buffers for proper device configuration.

What's inside

• Pin Type
• Supply and Reference Pins
• Dedicated Configuration STAG Pins
• VCCINT Power Requirements
• VCCIO Voltage Levels
• VCCPD Dedicated Power
• Ground Connections
• Input Reference Voltage (VREF)
• PLL Power Supplies
• No Connect Pins

Specifications

Frequently asked questions

Are these pin connection guidelines considered a formal specification?

No, the guidelines are considered preliminary and should only be used as a recommendation.

How should unused VREF pins be connected?

If not used, designers should connect them to either the VCCIO in the bank or GND.