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This document provides preliminary pin-out information for the Cyclone II EP2C5 Field Programmable Gate Array (FPGA). It details the electrical connections, bank assignments, and specific functions for each pin across various configuration modes.
The guidelines cover multiple data bus widths (x8/x9, x16/x18) and include definitions for Differential Clocks (DPCLK), Data Strobe signals (DQS), Test Logic pins (TCK, TMS, TDI, TDO), and Configuration status indicators. Users are advised that these guidelines are recommendations only and should be verified against the official datasheet before use in a design.
No, the pin connection guidelines are considered preliminary and should only be used as a recommendation.
The document version is 2.0.