This document provides design guidelines for Altera Corporation's HardCopy series devices. These devices offer cost savings, performance improvement, and reduced power consumption compared to their programmable counterparts. The document describes common design situations to avoid and provides alternatives for designing in these situations.
This document outlines the design rules necessary to ensure a smooth migration from FPGA devices to the equivalent HardCopy series devices. It emphasizes meeting specific coding styles and utilizing the Design Assistant tool within Quartus II software to check for potential issues early in the design process.
The text details methods for transferring data between asynchronous clock domains, which occur when clock signals lack a synchronous relationship. Recommended techniques include using double synchronizers for single-bit transfers, FIFO buffers for data bus signals requiring temporary storage, and handshake protocols for cases where memory resources are limited.
The four severity levels are Critical, High, Medium, and Information only.
A double synchronizer is recommended only if single-data signals need to be transferred across clock domains.