This document is a guide and checklist for power distribution network (PDN) design in high-speed board design. It describes the step-by-step tutorial and best-practice guidelines for designing and reviewing a PDN using the Frequency Domain Target Impedance Method. The document also introduces the Decoupling Design Tool provided by Altera for selecting decoupling capacitors in PDN design. Additional PDN-related papers and online lectures are mentioned as further resources. Familiarity with the mentioned tools and support collateral is assumed.
This document serves as a tutorial and checklist for designing power distribution networks (PDNs) for high-speed boards, specifically referencing Altera Stratix II GX FPGAs. It outlines best practices for calculating target impedance, selecting voltage regulator modules, and determining decoupling capacitance values across different frequency ranges.
The document uses the Frequency Domain Target Impedance Method.
Altera recommends using 50 percent of the maximum current as an estimation for the transient current.
For Stratix II GX FPGAs, use 50 MHz for Vcc and 200 MHz for all other power rails.